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ultra source technology corp. ltd. ?h?? ?h?? ?h?? ?h??1 50 1 50 1 50 1 50 ? ? ? ?1 7 1 7 1 7 1 7 tel : 886-2-82263168 fax : 886-2-82263353 ? ? ? ? 17f. no.150jian-yi rd, chung-ho, taipei 235, taiwan r.o.c. ` . ? ? 94 1 5 ? ?Y???? ? a2v64s4 0 dtp a2v64s4 0 dtp a2v64s4 0 dtp a2v64s4 0 dtp- - - - 7 pp 7 pp 7 pp 7 pp I? ? ? ? ? #66 0 8 #66 0 8 #66 0 8 #66 0 8 ew?J ?aS : (psc) ?J? A2V56S20BTP a2v56s30btp a2v56s40btp 256mb sdram specification 256mb sdram specification 256mb sdram specification 256mb sdram specification 256mb sdram specification powerchip semiconductor corp. no.12, li-hsin rd.1, science-based industrial park, hsin-chu taiwan, r.o.c. tel: 886-3-5795000 fax: 886-3-5792168 n o v . 2 0 0 3 r e v . 1 . 1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram a 2 v 5 6 s 2 0 b t p ( 4 - b a n k x 1 6 , 7 7 7 , 2 1 6 - w o r d x 4 - b i t ) a 2 v 5 6 s 3 0 b t p ( 4 - b a n k x 8 , 3 8 8 , 6 0 8 - w o r d x 8 - b i t ) a 2 v 5 6 s 4 0 b t p ( 4 - b a n k x 4 , 1 9 4 , 3 0 4 - w o r d x 1 6 - b i t ) powerchip semiconductor corp. frequency order part number package pb-free low power and pb-free 400mil tsop-2 type standard low power 400mil tsop-2 speed(ns) -6 -6l -g6 -g6l 166mhz a2v56s20/30/40 btp 6 -7 -7l -g7 -g7l 143mhz a2v56s20/30/40 btp 7 -75 -75l -g75 -g75l 133mhz a2v56s20/30/40 btp 7.5 400mil tsop-2 a2 v 56 s 3 0 tp -7 access item -75 : 7.5ns ( 133m h z /3-3-3) -8 : 8 ns (100 mhz/2-2-2) package type tp : tsop(ii) process generation interface v :lvttl organization 2 : x 4 , 3 : x8, 4: x16 synchronous dram density 56 :256mbit function 0 : random column psc dram -7 : 7 ns (143mhz/3-3-3) b a : 2nd generation , b:3rd generation -6 : 6ns ( 166m h z /3-3-3) -8 -8l -g8 -g8l 125mhz a2v56s20/30/40 btp 8 400mil tsop-2 t ype designation code ordering informa tion nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. a2v56s20atp (4-bank x 16,777,216-word x 4-bit) a2v56s30atp (4-bank x 8,388,608-word x 8-bit) a2v56s40atp (4-bank x 4,194,304-word x 16-bit) description A2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit synchronous dram with lvttl interface and a2v56s30btp is organized as 4-bank x 8,388,608-word x 8-bit and a2v56s40btp is organized as 4-bank x 4,194, 304-word x 16-bit. all inputs and outputs are referenced to the rising edge of clk. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,6084-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram page -1 - single 3.3v 0.3v power supply - max. clock frequency: -6:166mhz<3-3-3>/-7e:143mhz<2-2-2>/-7:143mhz<3-3-3>/-75:133mhz<3-3-3>/-8:100mhz<2-2-2> - fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by ba0,ba1(bank address) - /cas latency- 2/3 (programmable) - burst length- 1/2/4/8/fp (programmable) - burst type- sequential and interleave burst (programmable) - byte control- dqml and dqmu (a2v56s40btp) - random column access - auto precharge / all bank precharge controlled by a10 - auto and self refresh - 8192 refresh cycles /64ms(4 banks concurrent refresh) - lvttl interface - row address a0-12 /column address a0-9 , 11(x4) / a0-9(x8) / a0-8(x16) - package 400-mil, 54-pin thin small outline (tsop ii) with 0.8mm lead pitch A2V56S20BTP,a2v56s30btp and a2v56s40btp achieve very high speed clock rates up to 166mhz, and are suitable for main memories or graphic memories in computer systems. features item tclk tras trcd tac trc icc1 icc6 clock cycle time active to precharge command period (min.) row to column delay access time from clk ref /active command period operation current (single bank) self refresh current v56s20 cl=2 cl=3 cl=2 cl=3 v56s30 v56s40 (min.) (min.) (max.) (max.) (min.) (max.) -8 70 10 48 20 6 6 8 95 100 120 3 -6,-7e,-7,-75,-8 a2v56s20/30/40btp ma ns ns ns ns ns ma ma ma ns ns unit -7e 63 20 5.4 45 7 7 5.4 3 100 110 130 -75 67.5 10 45 20 5.4 7.5 6 3 100 110 130 -7 63 20 5.4 45 7 - - 3 100 110 130 -6 3 60 42 6 15 5 - - 100 110 130 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page- 2 pin configuration (top view) c lk : master clock c ke : clock enable / cs : chip select / ras : row address strobe / cas : column address strobe / we : write enable dq0-15 : data i/o dqm, dqmu/l : output disable / write mas k a0-12 : address input ba0,1 : bank address input vdd : power supply vddq : power supply for output vss : ground vssq : ground for output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 400mil x 875mil 54pin 0.8mm pitch tsop(ii) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc dqmu clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd dqml /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd A2V56S20BTP a2v56s30btp a2v56s40btp n o v . 2 0 0 3 r e v . 1 . 1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. a 2 v 5 6 s 2 0 b t p ( 4 - b a n k x 1 6 , 7 7 7 , 2 1 6 - w o r d x 4 - b i t ) a 2 v 5 6 s 3 0 b t p ( 4 - b a n k x 8 , 3 8 8 , 6 0 8 - w o r d x 8 - b i t ) a 2 v 5 6 s 4 0 b t p ( 4 - b a n k x 4 , 1 9 4 , 3 0 4 - w o r d x 1 6 - b i t ) a2 v 56 s 3 0 tp -7 access item -75 : 7.5ns ( 133m h z /3-3-3) -8 : 8 ns (100 mhz/2-2-2) package type tp : tsop(ii) process generation interface v :lvttl organization 2 : x 4 , 3 : x8, 4: x16 synchronous dram density 56 :256mbit function 0 : random column psc dram address buffer a0-12 ba0,1 control signal buffer / c s /ras /cas /we clk cke clock buffer control circuitry i/o buffer dq0-7 mode register dqm memory array bank #0 8192x1024x8 cell array memory array bank #1 cell array memory array bank #2 cell array memory array bank #3 cell array note:this figure shows the a2v56s30 b tp the a2v56s20 b tp configuration is 8192x2048x4 of cell array and dq0-3 the a2v56s40 b tp configuration is 8192x512x16 of cell array and dq0-15 -7 : 7 ns (143mhz/3-3-3) 8192x1024x8 8192x1024x8 8192x1024x8 b a : 2nd generation , b:3rd generation -7e : 7 ns (143mhz/2-2-2) -6 : 6ns ( 166 mh z /3-3-3) p a g e - 3 block diagram type designation code nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -4 pin function clk input master clock: all other inputs are referenced to the rising edge of clk cke input clock enable: cke controls internal clock.when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self-refresh. after self-refresh mode is started, cke becomes asynchronous input. self-refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9,11(x4)/a0-9(x8)/a0-8(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre , read , write commands. input / output input din mask / output disable: when dqm(u/l) is high in burst write, din for the current cycle is masked. when dqm(u/l) is high in burst read, dout is disabled at the next but one cycle. vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. data in and data out are referenced to the rising edge of clk. dq0-3(x4), dq0-7(x8), dq0-15(x16) dqm(x4,x8), dqmu/l(x16) nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page- 5 activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this com- mand also terminates burst read / write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. basic functions the a2v56s20 , 30 and 40 btp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh opt ion, and precharge option, respectively . to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @ refresh command a10 precharge option @ precharge or read/write command clk define basic command nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -6 command truth table note: 1. a7-9,11-12=l, a0-a6 =mode address h=high level, l=low level, v=valid, x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 deselect desel h x h xxxxxx no operation nop h x l hhhxxx row address entry & bank activate act hxl l hhvvv single bank precharge pre h x l l h l v l x precharge all banks prea h x l l h l h x column address entry & write write h x l h l l v l v column address entry & write with auto-precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto-precharge reada h x l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l hhxxxxxx l hl hhhxxx burst terminate tbst h x l h h l x x x mode register set mrs h x l lllllv x note 1 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -7 function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 llll op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l x tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal llll op-code, mode-add mrs illegal read h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal llll op-code, mode-add mrs illegal nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page- 8 function truth table (continued) current state /cs /ras /cas /we address command action write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal llll op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -9 function truth table (continued) current state /cs /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after trp) l l l h x refa illegal llll op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -10 function truth table (continued) current state /cs /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal llll op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal llll op-code, mode-add mrs illegal abbreviations: h =high level, l=low level, x=don't care b a=bank address, ra=row address, ca=column address, nop=no operation notes: 1 . all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2 . illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3 . must satisfy bus contention, bus turn around, write recovery requirements. 4 . nop to bank precharging or in idle state. may precharge bank indicated by ba. 5 . illegal if any bank is not idle. i llegal = device operation and/or data-integrity are not guaranteed. nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page- 11 function truth table (continued) current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain power down) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend abbreviations: h =high level, l=low level, x=don't care notes: 1 . cke low to high transition will re-enable clk and other inputs . a minimum setup time must b e satisfied before any command other than exit. 2 . self-refresh can be entered only from the all banks idle state. 3 . must be legal command. asynchronously nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -12 simplified state diagram refs self refresh ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence clk suspend mode register set idle auto refresh write suspend write writea suspend writea power on pre charge reada read read suspend row active power down reada suspend term term nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) /cs /ras /cas /we ba0,1 a12-a0 clk v r: reserved for future use ba0 ba1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 sw 0 0 ltmode bt bl burst length bl bt=0 bt=1 0 0 0 0 0 1 0 1 0 0 1 1 10 0 10 1 11 0 11 1 1 2 4 8 r r r full page 1 2 4 8 r r r r 0 1 burst type sequential interleaved latency mode cl /cas latency 0 0 0 0 0 1 0 1 0 0 1 1 10 0 10 1 11 0 11 1 r r 2 3 r r r r burst write single write sw 0 1 page -13 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 200s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -14 a2 a1 a0 initial address bl sequential interleaved column addressing 000 001 010 011 100 101 110 111 -00 -01 -10 -11 --0 0123456701234567 1234567010325476 2345670123016745 3456701232107654 4567012345670123 5670123454761032 6701234567452301 7012 0123 1230 2301 30 01 7654 0123 1032 2301 32 01 --1 12 10 3456 3210 10 10 8 4 2 command address clk read y write y /cas latency burst length burst length dq burst type cl= 3 bl= 4 q0 q1 q2 q3 d0 d1 d2 d3 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -15 operational description bank activate the sdram has four independent banks. each bank is activated by the act command with the bank ad- dresses (ba0,1). a row is indicated by the row ad- dresses a0-12. the minimum activation interval be- tween one bank and the other bank is trrd.multiple banks can be active state concurrently by issuing mul- tiple act commands. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea, pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued.ba0-1 are ?don?t care? in this case. read after trcd from the bank activation, a read command can be issued. 1st output data is avail- able after the /cas latency from the read, fol- lowed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a0-a9,a11(x4), a0-9(x8), a0-8(x16) , and the ad- dress sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl after reada. the next act command can be issued after (bl + trp) from the previous reada. in any case, trcd+bl trasmin must be met. bank activation and precharge all (bl=4, cl=3) clk command a 0-9,11-12 a10 ba0-1 dq act read act pre act xa xb yb xa 1 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trrd trcd trp xa precharge all nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -16 clk command a 0-9,11-12 a10 ba0-1 dq act act xa xa xa 00 00 trcd trp xa read with auto-precharge (cl=2, bl=4) read ya 1 00 qa0 qa1 qa2 qa3 internal precharge starts bl clk command dq act act trcd auto-precharge timing (read, bl=4) read qa0 qa1 qa2 qa3 internal precharge starts bl dq qa0 qa1 qa2 qa3 cl=2 cl=3 clk command a 0-9,11-12 a10 ba0-1 dq act read act pre act xa xb yb xa 0 xa xb 0 00 01 01 00 qb0 qb1 qb2 qb3 trcd trcd trp xa multi bank interleaving read (cl=2, bl=4) read ya 0 00 qa0 qa1 qa2 qa3 00 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -17 write a write command can be issued to any active bank. the start address is specified by a0-9,11(x4),a0-9(x8), a0-8(x16). 1st input data is set at the same cycle as the write. the consecutive data length to be write is defined by the burst length. the address sequence of burst data is defined by burst type. minmum delay time of a write command after an act command to the same bank is trcd. from the last input data to the pre command , the write recovery time (twr) is required. when a10 is high at a write command , auto-precharge (writea) is performed. any com- mand (read,write,pre,act,tbst) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at twr after the last input data cycle . the next act command can be issued after (bl+twr-1+trp) from the previous writea. in any case, trcd+bl+twr-1 trasmin must be met. clk command a 0-9,11-12 a10 ba0-1 dq act pre act xa xa 0 xa 00 00 trcd trp xa write (bl=4) write ya 0 00 da0 da1 da2 da3 bl twr clk command a 0-9,11-12 a10 ba0-1 dq act act xa xa xa 00 00 trcd trp xa write with auto-precharge (bl=4) write ya 1 00 da0 da1 da2 da3 bl twr internal precharge starts nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. clk command a 0-9,11-12 a10 ba0-1 dq read yb 0 00 qc0 qc1 qc2 qc3 read interrupted by read (cl=2, bl=4) read ya 0 00 qa0 qa1 qa2 qb0 read yc 0 10 clk command a 0-9,11-12 a10 ba0-1 dq act xa xa 00 read interrupted by write (cl=2, bl=4) read ya 0 00 qa0 da0 da1 da2 dqm write ya 0 00 da3 output disable by dqm by write page -18 burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed read to read interval is minimum 1 clk.. [ read interrupted by write ] burst read operation can be interrupted by write of any bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 2 cycle after write assertion. nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -19 [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=4. read interrupted by precharge (bl=4) clk command dq pre read q0 q1 q2 command dq pre read q0 q1 command dq pre read q0 command dq pre read q0 q1 q2 command dq pre read q0 q1 command dq pre read q0 c l=2 c l=3 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page- 20 [read interrupted by burst terminate] similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. the terminated bank remains active. read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. clk command dq tbst read q0 q1 q2 command dq tbst read q0 q1 command dq tbst read q0 command dq tbst read q0 q1 q2 command dq tbst read q0 q1 command dq tbst read q0 c l=2 c l=3 read interrupted by terminate (bl=4) nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) write interrupted by write (bl=4) clk command a 0-9,11-12 a10 ba0-1 dq write yb 0 00 dc0 dc1 dc2 dc3 write ya 0 00 da0 da1 da2 db0 write yc 0 10 clk command a0-9,11-12 a10 ba0-1 dq act xa xa 00 write interrupted by read (cl=2, bl=4) read yb 0 00 da0 da1 qb0 write ya 0 00 qb1 qb2 qb3 don't care page -21 [ write interrupted by write ] burst write operation can be interrupted by new write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. clk command a 0-9,11-12 a10 ba0-1 dq write ya 0 00 write interrupted by precharge (bl=4) act xa 0 00 da0 da1 pre 0 00 act xa 0 00 twr trp dqm clk command a 0-9,11-12 a10 ba0-1 dq write ya 0 00 write interrupted by terminate (bl=4) act xa 0 00 da0 da1 tbst write yb 0 00 db0 db1 db2 db3 page -22 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. [write interrupted by burst terminate] burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -23 [write with auto-precharge interrupted by write or read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after(bl+twr-1+ trp) from the writea. auto-precharge interruption by a command to the same bank is inhibited. writea interrupted by write to another bank (bl=4) clk command a 0-9,11-12 a10 ba0-1 dq db0 db1 db2 db3 write ya 1 00 da0 da1 write yb 0 10 bl twr trp act xa xa 00 interrupted auto-precharge activate writea interrupted by read to another bank (cl=2, bl=4) clk command a 0-9,11-12 a10 ba0-1 dq write ya 1 00 da0 da1 read yb 0 10 bl twr trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page -24 [read with auto-precharge interrupted by read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after (bl+trp) from the reada. auto-precharge interruption by a command to the same bank is inhibited. [full page burst] full page burst length is available for only the sequential burst type. full page burst read or write is repeated untill a precharge or a burst terminate command is issued. in case of the full page burst, a read or write with auto-precharge command is illegal. [single write] when single write mode is set, burst length for write is always one, independently of burst length defined by (a2-0). reada interrupted by read to another bank (cl=2, bl=4) clk command a 0-9,11-12 a10 ba0-1 dq read ya 1 00 qa0 qa1 read yb 0 10 bl trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page -25 auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 8192 refa cycles within 64ms refresh 256m bit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in the idle state. auto-refresh to auto- refresh interval is minimum trfc. any command must not be supplied to the device before trfc from the refa command. auto-refresh clk /cs /ras /cas /we cke a 0-12 b a0-1 auto refresh on all banks nop or deselect auto refresh on all banks minimum trfc nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-26 self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input . all other inputs including clk are disabled and ignored, so that power consumption due to synchro- nous inputs is saved. to exit the self-refresh, supply- ing stable clk inputs, asserting desel or nop com- mand and then asserting cke=h. after trfc from the 1st clk egde following cke=h, all banks are in the idle state and a new command can be issued, but desel or nop commands must be asserted till then. self-refresh clk /cs /ras /cas /we cke a 0-12 b a0-1 self refresh entry self refresh exit x 00 new command minimum trfc for recovery stable clk nop nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-27 clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. power down by cke clk c ommand cke c ommand cke standby power down active power down pre nop nop nop nop nop nop act dq suspend by cke clk c ommand dq cke write read d0 d1 d2 d3 q0 q1 q2 q3 ext.clk cke int.clk tih tis tih tis nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-28 dqm control dqm is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm(u,l) masks input data word by word. dqm(u,l) to write mask latency is 0. during reads, dqm(u,l) forces output to hi-z word by word. dqm(u,l) to output hi-z latency is 2. dqm function clk c ommand dq dqmu/l masked by dqmu/l=h disabled by dqmu/l=h write read d0 d2 d3 q0 q1 q3 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-29 absolute maximum ratings capacitance recommended operating conditions symbol parameter limits unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss 0 0 vddq supply voltage for output 3.0 3.3 3.6 v vssq 0 0 vih*1 high-level input voltage all inputs 2.0 vddq +0.3 v vil*2 low-level input voltage all inputs -0.3 0.8 v symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 - 4.6 v vddq supply voltage for output -0.5 - 4.6 v vi input voltage -0.5 - 4.6 v vo output voltage -0.5 - 4.6 v io output current 50 ma pd power dissipation ta = 25?c 1000 topr operating temperature 0 - 70 tstg storage temperature -65 - 150 with respect to vssq with respect to vss with respect to vssq symbol parameter test condition limits (max.) unit ci(a) input capacitance, address pin 5.0 pf ci(c) input capacitance, contorl pin @ 1mhz 1.4v bias 200mv swing vcc=3.3v 5.0 pf ci(k) input capacitance, clk pin 4.0 pf ci/o input capacitance, i/o pin 6.5 pf (ta=0 - 70 ?c ,unless otherwise noted) (ta=0 -7 0 ?c,vdd=vddq=3.3 ?.3v,vss=vssq=0v,unless otherwise noted) limits (min.) 2.5 2.5 2.5 4.0 3.8 3.8 3.5 6.5 -6/-7e/-7 -75/-8 supply voltage supply voltage for output ?c ?c 0 v v mw nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-30 average supply current from vdd ac operating conditions and characteristics note: 1.address are changed 3 times during trc , only 1 bank is active & all other banks are idle 2.all banks are idle 3.input signals are changed one time during 3x tclk 4.input signals are stable 5.all banks are active symbol parameter test conditions limits unit min. max. voh (dc) high-level output voltage (dc) ioh=-2ma 2.4 v vol (dc) low-level output voltage (dc) iol= 2ma 0.4 v ioz off-state output current q floating vo=0 -- vddq -10 10 ? input current vih = 0 -- vddq +0.3v -10 10 ? i i (ta=0 - 70 ?c, vdd=vddq=3.3 ?.3v,vss=vssq=0v, unless otherwise noted) symbol item limits (max.) organi- zation all bank active tclk = min bl=4, cl=3, iol=0ma icc4 burst current icc6 self-refresh current cke < 0.2v x4/x8/x16 -6,-7e,-7,,-75,-8 icc1 operating current trc=min, tclk=min bl=1,iol=0ma (ta=0 - 70 ?c, vdd=vddq=3.3 ?.3v,vss=vssq=0v, unless otherwise noted) icc5 trc=min, tclk=min auto-refresh current x4/x8/x16 precharge standby current in non-power down mode icc2n x4/x8/x16 cke=vilmax tclk=15ns icc2ns x4/x8/x16 cke=vihmin clk=vilmax(fixed) precharge standby current in power down mode icc2p x4/x8/x16 cke=vihmin tclk=15ns(note) icc2ps x4/x8/x16 cke=vihmin tclk=vilmax(fixed) icc3ns x4/x8/x16 cke=vihmin tclk=vilmax(fixed) icc3n x4/x8/x16 cke=/cs=vihmin tclk=15ns(note) x4 x8 x16 x4 x8 x16 unit active standby current -75 3 160 20 15 2 1 20 30 100 110 130 140 150 160 3 160 -8 20 15 2 1 20 30 95 100 120 110 120 130 -7e 3 160 20 15 2 1 20 30 100 110 130 140 150 160 ma ma ma ma ma ma ma ma ma ma ma ma ma ma note 2,4 2 3,5 5 4,5 1 2,3 -7 3 160 20 15 2 1 20 30 100 110 130 140 150 160 -6 3 160 20 15 2 1 20 30 100 110 130 140 150 160 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-31 ac timing requirements any ac timing is referenced to the input signal passing through 1.4v. input pulse levels:0.8v-2.0v input timing measurement level:1.4v clk dq 1.4v 1.4v symbol parameter limits unit -75 tclk clk cycle time cl=2 cl=3 tch clk high pulse width n tcl clk low pulse width n tt transition time of clk tis input setup time (all inputs) tih input hold time (all inputs) n trc row cycle time trcd row to column delay tras row a ctive time trp row precharge time twr write recovery time trrd act to act delay time trsc mode register set cycle time tref refresh interval time -8 (ta=0 - 70 ?c, vdd=vddq=3.3 ?.3v,vss=vssq=0v, unless otherwise noted) max. 10 7.8 120k max. 10 7.8 120k trfc refresh cycle time min. 10 7.5 2.5 1.8 1 2.5 1 67.5 45 20 15 15 15 20 75 2 1 min. 10 8 3 3 1 70 48 20 20 20 20 20 80 ns ns s s ns s us ns ns ns ns ns ns ns ns ns -7e max. 10 7.8 120k min. 7 2.5 2.5 1.8 1 1 63 45 20 14 14 14 20 70 7 max. 10 7.8 120k min. 7 2.5 2.5 1.8 1 1 63 45 20 14 14 14 20 70 - -7 -6 10 max. 7.8 120k min. 2 1.8 1 1 60 6 2 - 15 42 15 12 12 12 60 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. note: 1. if clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter. v out 50pf output timing measurement reference point clk 1.4v 1.4v dq symbol parameter limits unit -75 -8 tac access time from clk cl=2 ns cl=3 ns toh output hold time from clk max. 6 5.4 5.4 ns tolz delay time , output low- impedance from clk ns ns tohz ns note *1 tohz tac clk dq 1.4v 1.4v toh tolz cl=2 cl=3 min. 3 3 3 0 (ta=0 - 70 ?c, vdd=vddq=3.3 ?.3v,vss=vssq=0v, unless otherwise noted) delay time , output high- impedance from clk max. 6 6 6 3 0 3 min. 3 -7e max. 5.4 5.4 min. 0 2.7 2.7 -7 max. 5.4 5.4 5.4 min. 0 2.7 2.7 2.7 -6 max. 5 5 2.5 0 2.5 min. page-32 switching characteristics output load condition nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-33 burst write (single bank) [bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc trcd tras twr trp trcd twr italic paramater shows minimum case act#0 write#0 pre#0 act#0 write#0 pre# 0 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-34 burst write (multi bank) [bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc trcd tras twr trp trcd twr italic paramater shows minimum case act#0 write#0 pre#0 act#0 write#0 pre# 0 x x x 1 act#1 trrd trcd y 1 d1 d1 d1 d1 writea#1 (auto-precharge) act#1 x x x 1 trc nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-35 burst read (single bank) [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 q0 q0 q0 q0 0 x y x x 0 0 q0 q0 q0 q0 0 trc trcd tras trp trcd italic paramater shows minimum case act#0 read#0 pre#0 act#0 read#0 pre#0 tras nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-36 burst read (multi bank) [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 q0 q0 q0 q0 1 x y x x 0 0 q0 q0 q0 q0 0 trc trcd trcd italic paramater shows minimum case act#0 reada#0 reada#1 act#0 read#0 pre#0 x x x 1 trrd act#1 y q1 q1 q1 q1 trcd x x x 1 act#1 trc tras nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-37 write interrupted by write [bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 d0 d0 1 y 0 d0 d0 d0 d0 0 trcd italic paramater shows minimum case act#0 write#0 write#0 pre#0 x x x 1 trrd act#1 y d0 d1 d1 d1 x x x 1 act# 1 y 0 write#0 writea#1 interrupt same bank interrupt other bank interrupt other bank twr nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-38 read interrupted by read [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 q0 q0 1 y 0 q1 q1 q0 q0 trcd italic paramater shows minimum case act#0 read#0 read#0 x x x 1 trrd act#1 y q0 q1 q1 q1 x x x 1 act#1 y 1 read#1 reada#1 interrupt other bank trcd interrupt same bank interrupt other bank q0 q0 nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-39 write interrupted by read, read interrupted by write [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 y 1 d1 d1 d1 d1 1 trcd italic paramater shows minimum case act#0 write#0 write#1 pre#1 x x x 1 trrd act#1 q1 q1 y 1 twr read#1 trcd nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-40 write / read terminated by precharge [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd italic paramater shows minimum case act#0 write#0 read#0 pre#0 0 pre#0 twr x x x 0 act#0 trp 0 tras trcd trp x x x act#0 trc terminate terminate nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-41 write / read terminated by burst terminate [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd italic paramater shows minimum case act#0 write#0 read#0 tbst pre#0 y 0 tbst d0 d0 d0 d0 write#0 twr nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-42 single write burst read [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 q0 q0 trcd italic paramater shows minimum case act#0 write#0 read#0 q0 q0 y 0 nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-43 power-up sequence and intialize c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 0 italic paramater shows minimum case pre all refa act#0 mrs refa 0 0 0 ma x x x 200 s refa trp trfc minimum 8 refa cycles nop trfc trsc power on nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-44 auto refresh c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 italic paramater shows minimum case pre all refa y 0 d0 d0 d0 d0 write#0 x x x 0 act#0 trp trfc trcd all banks must be idle before refa is issued. nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-45 self refresh c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 italic paramater shows minimum case pre all self refresh entry self refresh exit x x x 0 act#0 trp all banks must be idle before refs is issued. trfc nov.2003 rev.1 .1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) powerchip semiconductor corp. page-46 clk suspension [cl=2, bl=4] c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 x x x 0 y 0 d0 q0 q0 trcd italic paramater shows minimum case act#0 write#0 read#0 q0 y 0 d0 d0 d0 internal clk suspended q0 internal clk suspended nov.2003 rev.1.1 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram 256mb synchronous dram powerchip semiconductor corp. A2V56S20BTP (4-bank x 16,777,216-word x 4-bit) a2v56s30btp (4-bank x 8,388,608-word x 8-bit) a2v56s40btp (4-bank x 4,194,304-word x 16-bit) page-47 power down c lk / cs / ras / cas / we c ke d qm a 0-9,11 a 10 a 12 b a0,1 d q 012345678910111213141516 italic paramater shows minimum case pre all act#0 x 0 x x standby power down active power down |
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